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  Apple's new blazingly fast Power Mac G4 capable of processing millions of instructions per second requires ultra fast 100 mhz SDRAM operating at maximum speed to deliver super computer performance. The following article explains how utilizing the 100 mhz SDRAM maximum speed code achieves the maximum performance of the G4.The most advanced PC-100 is an intel SDRAM specification that outlines the SDRAM timing and functional parameter of memory modules operating at a 100 Mhz bus speed. The Intel PC-100 document defines timing characteristics of memory chips (SDRAMs) and memory boards for 100 Mhz operation. This document details the differences between the JEDEC standard and PC100 SDRAM timing and functional specifications. The first mainstream shift to improve the memory bus speed from 66MHz to 100MHz was initiated by Intel. Intel published, and subsequently revised, an SDRAM specification that defined in great detail AC and DC timing parameters necessary for 100MHz operation in a PC environment. This specification was based on simulated timing analysis of a 4-slot PC system (2 physical SDRAM banks per slot) running the memory bus at 100MHz. The 100MHz SDRAM was designed to improve memory bandwidth. It synchronizes the internal operation of the DRAM to a system clock to achieve higher memory bandwidth. |
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Understanding SDRAM Speed Codes requires familiarity with internal SDRAM I/O operation. Every SDRAM physical bank is comprised of four internal banks , each internal bank has its own clock synchronized with the system clock. When one bank is active and switches to the adjacent bank for I/O, there is a delay caused by this "switching", The CPU has to wait until the "switching" is completed, the longer the switching, the slower the SDRAM operation. This factor is significant when processing large amounts of files or data. For instance the slowest speed code (3-3-3) means that during internal SDRAM I/O, switching from one internal SDRAM bank to another internal SDRAM bank, the CPU has to wait 3 clock cycles compared with the maximum speed code (2-2-2) of SDRAM memory, where the CPU has to wait for 2 clock cycles to complete the internal bank switching. The figure below illustrates the internal SDRAM operation and speed codes. |
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This Tech note is written to help users understand the SDRAM speed code and maximized their memory subsystem in new Apple G4 and G3s. Please check back later for a new article on maximizing storage subsystems in new G4s and G3s. |
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